Digital-to-analog conversion (DAC) circuits are used for converting digital signals into analog signals. Generally, a DAC circuit may adopt either a string configuration or a ladder configuration. A DAC circuit adopting the string configuration tends to be space efficient and power efficient, but it is more susceptible to the distortion caused by process mismatch. By contrast, a DAC circuit adopting the ladder configuration tends to be less sensitive to process mismatch, but it comes with the cost of increased layout areas and power consumption.
Attempts have been made in the past to combine the string configuration with the ladder configuration. These combinations generally involve a voltage driven string circuit followed by a ladder circuit. Because the string circuit is driven by a constant voltage source, the string circuit needs additional output buffers to minimize integral non-linearity (INL) errors and differential non-linearity (DNL) errors. The additional output buffers increase the power consumption and layout size of the overall DAC circuit. In a DAC system that implements multiple conversion channels, the cost of including the additional output buffers can be prohibitively high. Thus, there is a need for a DAC system that provides high precision but without incurring the cost of additional output buffers.